The present invention relates generally to semiconductor device manufacturing and more particularly to methods of manufacturing flash memory devices.
Flash memory devices are a type of EEPROM (Electrically Erasable Programmable Read-Only Memory). The term xe2x80x9cflashxe2x80x9d refers to the ability of the memory to be erased in blocks. As in other non-volatile memory devices, flash memory devices typically store electrical charges, representing data, in transistors having either a floating-gate or a charge-trapping dielectric. The stored charges affect the threshold voltage of the transistors. For example, in an n-channel floating-gate transistor an accumulation of electrons in the floating-gate electrode creates a high threshold voltage in the transistor. The presence or absence of the stored charge can be determined by whether current flows between a source region and a drain region of the transistor when appropriate voltages are applied to the control gate, source, and drain.
While there are myriad ways of configuring flash memory devices, in one common configuration sometimes called a NOR architecture, the drain regions of each memory cell (transistor) have a contact and are connected in rows forming bit lines in a conductive layer that runs above the memory cell stacks. The conductive layer can be, for example, a first metal layer. Source regions are typically connected by Vss lines running parallel to the word lines and leading to a common ground. The Vss lines are formed by doping the semiconductor substrate.
This configuration has proven useful in building compact, high-speed flash memory devices, however, there has been a continuous demand to further reduce the size of these devices. In further reducing the size of flash memory devices, the resistance in Vss lines has become an issue. As attempts are made to make smaller devices, it is found that the amount and depth of doping required to adequately lower resistance along Vss lines cannot be introduced without causing short channel effects. Thus, there has been an unsatisfied need for methods of further reducing the Vss resistance in flash memory devices without causing short channel effects.
The following presents a simplified summary of the invention in order to provide a basic understanding of some of its aspects. This summary is not an extensive overview of the invention and is intended neither to identify key or critical elements of the invention nor to delineate its scope. The primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the invention relates to a method of manufacturing a flash memory device in which Vss lines are salicided prior to forming memory cell stacks. According to the invention, silicide is aligned to the Vss lines by a layer of temporary material, such as a silicon nitride layer, patterned to form dummy gates. A dielectric layer can be deposited and planarized with the dummy gates prior to their removal. The dielectric layer facilitates selective removal of the dummy gates and formation of memory cell stacks that are properly aligned with the Vss lines and drain regions. The dummy gate concept can be used with methods of forming low resistance Vss lines other than saliciding. One advantage of the invention is that the memory cell stacks are not exposed to high temperature processing used in forming low resistance Vss lines.
Other advantages and novel features of the invention will become apparent from the following detailed description of the invention and the accompanying drawings. The detailed description of the invention and drawings provide exemplary embodiments of the invention. These exemplary embodiments are indicative of but a few of the various ways in which the principles of the invention can be employed.